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High Accuracy Ultralow IQ, 500 mA anyCAP(R) Adjustable Low Dropout Regulator ADP3336
FUNCTIONAL BLOCK DIAGRAM
Q1 THERMAL PROTECTION IN OUT
FEATURES High Accuracy Over Line and Load: 0.9% @ 25 C, 1.8% Over Temperature Ultralow Dropout Voltage: 200 mV (Typ) @ 500 mA Requires Only CO = 1.0 F for Stability anyCAP = Stable with Any Type of Capacitor (Including MLCC) Current and Thermal Limiting Low Noise Low Shutdown Current: < 1.0 A 2.6 V to 12 V Supply Range 1.5 V to 10 V Output Range -40 C to +85 C Ambient Temperature Range Ultrasmall Thermally-Enhanced 8-Lead MSOP Package APPLICATIONS PCMCIA Card Cellular Phones Camcorders, Cameras Networking Systems, DSL/Cable Modems Cable Set-Top Box MP3/CD Players DSP Supply
ADP3336
CC FB DRIVER gm BANDGAP REF
SD
GND
ADP3336
OUT OUT IN VIN CIN 1F IN FB SD ON OFF GND R2 OUT R1 VOUT COUT 1F
GENERAL DESCRIPTION
The ADP3336 is a member of the ADP333x family of precision low dropout anyCAP voltage regulators. The ADP3336 operates with an input voltage range of 2.6 V to 12 V and delivers a continuous load current up to 500 mA. The ADP3336 stands out from conventional LDOs with the lowest thermal resistance of any MSOP-8 package and an enhanced process that enables it to offer performance advantages beyond its competition. Its patented design requires only a 1.0 F output capacitor for stability. This device is insensitive to output capacitor Equivalent Series Resistance (ESR), and is stable with any good quality capacitor, including ceramic (MLCC) types for spacerestricted applications. The ADP3336 achieves exceptional accuracy of 0.9% at room temperature and 1.8% over temperature, line, and load. The dropout voltage of the ADP3336 is only 200 mV (typical) at 500 mA. This device also includes a safety current limit, thermal overload protection and a shutdown feature. In shutdown mode, the ground current is reduced to less than 1 A. The ADP3336 has ultralow quiescent current 80 A (typical) in light load situations.
Figure 1. Typical Application Circuit
anyCAP is a registered trademark of Analog Devices Inc.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2000
ADP3336-SPECIFICATIONS1, 2(V
Parameter OUTPUT Voltage Accuracy3, 4 Symbol VOUT
IN
= 6.0 V, CIN = COUT = 1.0 F, TJ = -40 C to +125 C unless otherwise noted.)
Min -0.9 Typ Max +0.9 Unit %
Conditions VIN = VOUT(NOM) + 0.4 V to 12 V IL = 0.1 mA to 500 mA TJ = 25C VIN = VOUT(NOM) + 0.4 V to 12 V IL = 0.1 mA to 500 mA TJ = -40C to +125C VIN = VOUT(NOM) + 0.4 V to 12 V IL = 0.1 mA to 500 mA TJ = 150C VIN = VOUT(NOM) + 0.4 V to 12 V IL = 0.1 mA TA = 25C IL = 0.1 mA to 500 mA TA = 25C VOUT = 98% of VOUT(NOM) IL = 500 mA IL = 300 mA IL = 50 mA IL = 0.1 mA VIN = VOUT(NOM) + 1 V f = 10 Hz-100 kHz, CL = 10 F IL = 500 mA, CNR = 10 nF, VOUT = 2.5 f = 10 Hz-100 kHz, CL = 10 F IL = 500 mA, CNR = 0 nF, VOUT = 2.5 IL = 500 mA IL = 300 mA IL = 50 mA IL = 0.1 mA VIN = VOUT(NOM) - 100 mV IL = 0.1 mA SD = 0 V, VIN = 12 V ON OFF 0 SD 12 V TA = 25C, VIN = 12 V TA = 85C, VIN = 12 V
-1.8
+1.8
%
-2.3
+2.3
%
Line Regulation3
0.04
mV/V
Load Regulation Dropout Voltage VDROP
0.04
mV/mA
Peak Load Current Output Noise
ILDPK VNOISE
200 140 60 10 800 27 45
400 235 130
mV mV mV mV mA V rms V rms
GROUND CURRENT5 In Regulation
IGND
In Dropout In Shutdown SHUTDOWN Threshold Voltage SD Input Current Output Current In Shutdown
IGND IGNDSD VTHSD ISD IOSD
4.5 2.6 0.5 80 120 0.01 2.0 1.2 0.01 0.01
10 6 1.5 110 400 1
mA mA mA A A A V V A A A
0.4 5 1 1
NOTES 1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods. 2 Application stable with no load. 3 VIN = 2.6 V to 12 V for models with V OUT(NOM) 2.2 V. 4 Over the VOUT range of 1.5 V to 10 V. 5 Ground current includes current through external resistors. Specifications subject to change without notice.
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ADP3336
ABSOLUTE MAXIMUM RATINGS* PIN FUNCTION DESCRIPTIONS
Input Supply Voltage . . . . . . . . . . . . . . . . . . . -0.3 V to +16 V Shutdown Input Voltage . . . . . . . . . . . . . . . . -0.3 V to +16 V Power Dissipation . . . . . . . . . . . . . . . . . . . Internally Limited Operating Ambient Temperature Range . . . . -40C to +85C Operating Junction Temperature Range . . . -40C to +150C JA 2-layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153C/W JA 4-layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110C/W Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature Range (Soldering 10 sec) . . . . . . . . 300C Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220C
*This is a stress rating only; operation beyond these limits can cause the device to be permanently damaged.
Pin No.
Mnemonic
Function Output of the Regulator. Bypass to ground with a 1.0 F or larger capacitor. All pins must be connected together for proper operation. Ground Pin. Feedback Input. Connect to an external resistor divider which sets the output voltage. Can also be used for further reduction of output noise (see text for detail). Capacitor required if COUT > 3.3 F. Active Low Shutdown Pin. Connect to ground to disable the regulator output. When shutdown is not used, this pin should be connected to the input pin. Regulator Input. All pins must be connected together for proper operation.
1, 2, 3 OUT
4 5
GND FB
6
ORDERING GUIDE
SD
Model
Output Voltage
Package Package Description Option mini_SO RM-8
Branding Information LHA
7, 8
IN
ADP3336 ADJ
PIN CONFIGURATION
OUT 1 OUT 2
8
IN
IN TOP VIEW OUT 3 (Not to Scale) 6 SD GND 4
5
ADP3336
7
FB
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3336 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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ADP3336-Typical Performance Characteristics
2.202 2.201 IL = 0
OUTPUT VOLTAGE - Volts
2.201
140
VOUT = 2.2V VIN = 6V
VOUT = 2.2V
2.200 2.199 2.198 2.197 2.196 2.195 2.194 2.193
IL = 100 A 120
A GROUND CURRENT -
VOUT = 2.2V
OUTPUT VOLTAGE - Volts
2.200 2.199 150mA 2.198 2.197 300mA 2.196 2.195 2.194 2 4 6 8 10 INPUT VOLTAGE - Volts 12 500mA
100 80 60 40 20 0 IL = 0
0
100
200 300 400 OUTPUT LOAD - mA
500
0
2
4 6 8 10 INPUT VOLTAGE - Volts
12
TPC 1. Line Regulation Output Voltage vs. Supply Voltage
TPC 2. Output Voltage vs. Load Current
TPC 3. Ground Current vs. Supply Voltage
5.0 VIN = 6V VOUT = 2.2V
GROUND CURRENT - mA
0.5 0 0.4
GROUND CURRENT - mA
8 7 IL = 500mA VIN = 6V VOUT = 2.2V
4.0
OUTPUT CHANGE - %
300mA 0.3 0.2 0.1 500mA 0 -0.1 500mA
6 5 4 3 2 1 100mA 50mA 0 0 25 45 65 85 105 125 -40 -15 5 JUNCTION TEMPERATURE - C 300mA
3.0
2.0
1.0
0
0
-0.2
0 -40 -15 5 25 65 85 105 125 45 JUNCTION TEMPERATURE - C
100
200 300 400 OUTPUT LOAD - mA
500
TPC 4. Ground Current vs. Load Current
TPC 5. Output Voltage Variation % vs. Junction Temperature
TPC 6. Ground Current vs. Junction Temperature
250
VOUT - Volts
VOUT = 2.2V
INPUT/OUTPUT VOLTAGE - Volts
3.0 2.5 2.0 1.5
DROPOUT VOLTAGE - mV
200
VOUT = 2.2V SD = VIN RL = 4.4
3 2 1 COUT = 10 F 0 4 2 0 200 400 TIME - 600 s VOUT = 2.2V SD = VIN RL = 4.4 800 COUT = 1 F
150
100
0.5 0 1 2 3 TIME - Sec 4
50
0
0
100
200 300 400 OUTPUT LOAD - mA
500
TPC 7. Dropout Voltage vs. Output Current
TPC 8. Power-Up/Power-Down
VIN - Volts
1.0
TPC 9. Power-Up Response
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ADP3336
VOUT - Volts
VOUT - Volts
2.210 2.200 2.190 2.189 2.179 VOUT = 2.2V RL = 4.4 CL = 1 F
2.210 2.200 2.190 2.189 2.179 VOUT = 2.2V RL = 4.4 CL = 10 F
mA Volts
2.3 2.2 2.1
400 200 0 VIN = 6V VOUT = 2.2V CL = 1 F 200 400 600 TIME - s 800
VIN - Volts
VIN - Volts
3.500 3.000 40 80 140 TIME - s 180
3.500 3.000 40 80 140 TIME - s 180
TPC 10. Line Transient Response
TPC 11. Line Transient Response
TPC 12. Load Transient Response
2.3
2.2
Volts
3
VOUT
Volts
1F
2.2 2.1
0 FULL SHORT
2 1 0 10 F 1F
VIN = 6V VOUT = 2.2V RL = 4.4 10 F
3
400
A
800m SHORT
2
VOUT = 2.2V VIN = 6V CL = 10 F 200 400 600 TIME - s 800
mA
VSD
200 0
1 0 200 400 600 TIME - s
VIN = 4V
2 0 200 400 600 TIME - s 800
800
TPC 13 Load Transient Response
TPC 14. Short Circuit Current
TPC 15. Turn On-Turn Off Response
-20 -30
160 VOUT = 2.2V CL = 1 F IL = 500mA CL = 1 F IL = 50 A CL = 10 F IL = 500mA 140 120 VOUT = 2.0V CNR = 10nF
100
VOUT = 2.2V IL = 1mA CL = 10 F CL = 10 F CNR = 10nF CNR = 0
VOLTAGE NOISE SPECTRAL DENSITY - V/ Hz
RIPPLE REJECTION - dB
10
RMS NOISE - V
-40 -50 -60 -70 -80 -90 10 100
100 80 60 40
IL = 500mA WITHOUT NOISE REDUCTION IL = 500mA WITH NOISE REDUCTION IL = 0mA WITHOUT NOISE REDUCTION
1
CL = 1 F CNR = 0
0.1 CL = 1 F CNR = 10nF 0.01
CL = 10 F IL = 50 A 1k 10k 100k FREQUENCY - Hz 1M 10M
20 0 0
IL = 0mA WITH NOISE REDUCTION
10
20 CL -
30 F
40
50
0.001 10
100
1k 10k 100k FREQUENCY - Hz
1M
TPC 16. Power Supply Ripple Rejection
TPC 17. RMS Noise vs. CL (10 Hz-100 kHz)
TPC 18. Output Noise Density
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ADP3336
THEORY OF OPERATION
The new anyCAP LDO ADP3336 uses a single control loop for regulation and reference functions. The output voltage is sensed by a resistive voltage divider consisting of R1 and R2 which is varied to provide the available output voltage option. Feedback is taken from this network by way of a series diode (D1) and a second resistor divider (R3 and R4) to the input of an amplifier.
INPUT Q1 COMPENSATION CAPACITOR OUTPUT R1 CLOAD (a) RLOAD R2
superior line noise rejection and very high regulator gain, which leads to excellent line and load regulation. An impressive 1.8% accuracy is guaranteed over line, load, and temperature. Additional features of the circuit include current limit and thermal shutdown.
APPLICATION INFORMATION Capacitor Selection
NONINVERTING WIDEBAND DRIVER
gm
ATTENUATION (VBANDGAP /VOUT) R3 D1 PTAT FB VOS R4 PTAT CURRENT
ADP3336
GND
Output Capacitors: as with any micropower device, output transient response is a function of the output capacitance. The ADP3336 is stable with a wide range of capacitor values, types and ESR (anyCAP). A capacitor as low as 1 F is all that is needed for stability; larger capacitors can be used if high output current surges are anticipated. The ADP3336 is stable with extremely low ESR capacitors (ESR 0), such as multilayer ceramic capacitors (MLCC) or OSCON. Note that the effective capacitance of some capacitor types may fall below the minimum at cold temperature. Ensure that the capacitor provides more than 1 F at minimum temperature.
Input Bypass Capacitor
Figure 2. Functional Block Diagram
A very high gain error amplifier is used to control this loop. The amplifier is constructed in such a way that equilibrium produces a large, temperature-proportional input, "offset voltage" that is repeatable and very well controlled. The temperatureproportional offset voltage is combined with the complementary diode voltage to form a "virtual bandgap" voltage, implicit in the network, although it never appears explicitly in the circuit. Ultimately, this patented design makes it possible to control the loop with only one amplifier. This technique also improves the noise characteristics of the amplifier by providing more flexibility on the trade-off of noise sources that leads to a low noise design. The R1, R2 divider is chosen in the same ratio as the bandgap voltage to the output voltage. Although the R1, R2 resistor divider is loaded by the diode D1 and a second divider consisting of R3 and R4, the values can be chosen to produce a temperature stable output. This unique arrangement specifically corrects for the loading of the divider thus avoiding the error resulting from base current loading in conventional circuits. The patented amplifier controls a new and unique noninverting driver that drives the pass transistor, Q1. The use of this special noninverting driver enables the frequency compensation to include the load capacitor in a pole-splitting arrangement to achieve reduced sensitivity to the value, type, and ESR of the load capacitance. Most LDOs place very strict requirements on the range of ESR values for the output capacitor because they are difficult to stabilize due to the uncertainty of load capacitance and resistance. Moreover, the ESR value, required to keep conventional LDOs stable, changes depending on load and temperature. These ESR limitations make designing with LDOs more difficult because of their unclear specifications and extreme variations over temperature. With the ADP3336 anyCAP LDO, this is no longer true. It can be used with virtually any good quality capacitor, with no constraint on the minimum ESR. This innovative design allows the circuit to be stable with just a small 1 F capacitor on the output. Additional advantages of the pole-splitting scheme include
An input bypass capacitor is not strictly required but is advisable in any application involving long input wires or high source impedance. Connecting a 1 F capacitor from IN to ground reduces the circuit's sensitivity to PC board layout. If a larger value output capacitor is used, then a larger value input capacitor is also recommended.
Noise Reduction
A noise reduction capacitor (CNR) can be placed between the output and the feedback pin to further reduce the noise by 6 dB-10 dB (TPC 18). Low leakage capacitors in 100 pF-500 pF range provide the best performance. Since the feedback pin (FB) is internally connected to a high impedance node, any connection to this node should be carefully done to avoid noise pickup from external sources. The pad connected to this pin should be as small as possible and long PC board traces are not recommended. When adding a noise reduction capacitor, maintain a minimum load current of 1 mA when not in shutdown. It is important to note that as CNR increases, the turn-on time will be delayed. With CNR values greater than 1 nF, this delay may be on the order of several milliseconds.
ADP3336
IN VIN CIN 1F IN OUT OUT OUT FB CNR R1 VOUT COUT 1F
SD ON OFF GND
R2
Figure 3. Typical Application Circuit
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ADP3336
Output Voltage
The ADP3336 has an adjustable output voltage that can be set by an external resistor divider. The output voltage will be divided by R1 and R2, and then fed back to the FB pin. In order to have the lowest possible sensitivity of the output voltage to temperature variations, it is important that the parallel resistance of R1 and R2 is always 50 k. R1 x R2 = 50 k R1 + R2 Also, for the best accuracy over temperature the feedback voltage should be set for 1.178 V: R2 VFB = VOUT x R1 + R2 where VOUT is the desired output voltage and VFB is the "virtual bandgap" voltage. Note that VFB does not actually appear at the FB pin due to loading by the internal PTAT current. Combining the above equations and solving for R1 and R2 gives the following formulas:
DIE
Figure 4. Thermally Enhanced Paddle-Under-Lead Package
Thermal Overload Protection
The ADP3336 is protected against damage from excessive power dissipation by its thermal overload protection circuit which limits the die temperature to a maximum of 165C. Under extreme conditions (i.e., high ambient temperature and power dissipation) where die temperature starts to rise above 165C, the output current is reduced until the die temperature has dropped to a safe level. The output current is restored when the die temperature is reduced. Current and thermal limit protections are intended to protect the device against accidental overload conditions. For normal operation, device power dissipation should be externally limited so that junction temperatures will not exceed 150C.
Calculating Junction Temperature
R1 = 50 k x
VOUT VFB 50 k R2 = VFB 1 - VOUT
Device power dissipation is calculated as follows: PD = (VIN - VOUT) ILOAD + (VIN) IGND Where ILOAD and IGND are load current and ground current, VIN and VOUT are input and output voltages respectively. Assuming ILOAD = 400 mA, IGND = 4 mA, VIN = 5.0 V and VOUT = 3.3 V, device power dissipation is: PD = (5 - 3.3) 400 mA + 5.0(4 mA) = 700 mW The proprietary package used in the ADP3336 has a thermal resistance of 110C/W, significantly lower than a standard MSOP-8 package. Assuming a 4-layer board, the junction temperature rise above ambient temperature will be approximately equal to:
Table I. Feedback Resistor Selection
VOUT 1.5 V 1.8 V 2.2 V 2.7 V 3.3 V 5V 10 V
R1 (1% Resistor) 63.4 k 76.8 k 93.1 k 115 k 140 k 210 k 422 k
R2 (1% Resistor) 232 k 147 k 107 k 88.7 k 78.7 k 64.9 k 56.2 k
TJA = 0.700 W x 110C = 77.0C
To limit the maximum junction temperature to 150C, maximum allowable ambient temperature will be: TAMAX = 150C - 77.0C = 73.0C
Printed Circuit Board Layout Consideration
Paddle-Under-Lead Package
The ADP3336 uses a proprietary paddle-under-lead package design to ensure the best thermal performance in an MSOP-8 footprint. This new package uses an electrically isolated die attach that allows all pins to contribute to heat conduction. This technique reduces the thermal resistance to 110C/W on a 4-layer board as compared to >160C/W for a standard MSOP-8 leadframe. Figure 4 shows the standard physical construction of the MSOP-8 and the paddle-under-lead leadframe.
All surface mount packages rely on the traces of the PC board to conduct heat away from the package.
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ADP3336
In standard packages the dominant component of the heat resistance path is the plastic between the die attach pad and the individual leads. In typical thermally enhanced packages one or more of the leads are fused to the die attach pad, significantly decreasing this component. To make the improvement meaningful, however, a significant copper area on the PCB must be attached to these fused pins. The proprietary paddle-under-lead frame design of the ADP3336 uniformly minimizes the value of the dominant portion of the thermal resistance. It ensures that heat is conducted away by all pins of the package. This yields a very low 110C/W thermal resistance for an MSOP-8 package, without any special board layout requirements, relying only on the normal traces connected to the leads. This yields a 33% improvement in heat dissipation capability as compared to a standard MSOP-8 package. The thermal resistance can be decreased by, approximately, an additional 10% by attaching a few square cm of copper area to the IN pin of the ADP3336 package. It is not recommended to use solder mask or silkscreen on the PCB traces adjacent to the ADP3336's pins since it will increase the junction-to-ambient thermal resistance of the package.
Shutdown Mode
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead mini_SO (RM-8)
0.122 (3.10) 0.114 (2.90)
8
5
0.122 (3.10) 0.114 (2.90)
1 4
0.199 (5.05) 0.187 (4.75)
PIN 1 0.0256 (0.65) BSC 0.120 (3.05) 0.112 (2.84) 0.006 (0.15) 0.002 (0.05) 0.018 (0.46) SEATING 0.008 (0.20) PLANE 0.043 (1.09) 0.037 (0.94) 0.011 (0.28) 0.003 (0.08) 0.120 (3.05) 0.112 (2.84) 33 27
0.028 (0.71) 0.016 (0.41)
-8-
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PRINTED IN U.S.A.
C02174-2.5-10/00 (rev. 0)
Applying a TTL high signal to the shutdown (SD) pin or tying it to the input pin, will turn the output ON. Pulling SD down to 0.4 V or below, or tying it to ground will turn the output OFF. In shutdown mode, quiescent current is reduced to much less than 1 A.

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